A Trinidad engineer's answer to RISC-V's harshest critic: ISA elegance is what you afford after the chip reaches your desk

The RISC-V argument in two numbers: eleven cycles and ninety cents

Dmitry Grinberg's essay "RISC-V: They Should Have Known Better" and Armstrong Subero's reply to it end at the same place: a ten-cent microcontroller. Grinberg's piece reached the front page of Hacker News in mid-August 2026 and started what Subero calls a good argument on Lobsters 1 2. Before any interrupt arithmetic, Grinberg derives from first principles what a cheap microcontroller core needs, and the answer is RV32EC 3. Subero, an embedded engineer who works out of Trinidad and Tobago, builds on exactly that core, and his reply is built around a number the original essay never prices in: he pays US$60 to US$200 in freight for one-dollar parts that ship free to buyers in the United States and Europe 1.

Subero calls Grinberg's piece the most substantial criticism the architecture has had in a while, and he is no ISA apologist: he moved his own stack from STM32 and ARM parts to RISC-V and has hit the same rough edges himself, down to Zicsr being a separate thing you have to ask for 1. The fight is over what that proves, and it turns on geography.

The critic derived the chip, then objected to it

Grinberg's setup is careful. A cheap core, he argues, exists to prod registers inside a larger chip: an MP3 player, an SD card, a USB stick, one-time-use vapes 3. It needs low interrupt latency, a small die area, and dense code; it can drop the hardware divider, probably the multiplier, and all privilege separation 3. Then he stops himself: "But," you might say, "you just described RV32IC (or RV32EC)!" 3

He argues past his own punchline with a concession: "I am 100% sure that RISC-V will own the cheap-as-dirt single-use microcontroller space eventually." In his telling, it gets there despite the design, not because of it, taking over the 8051's old niche as a modest upgrade 3. Subero's summary of the move: "He derives the case for the chip and then spends the rest of the article annoyed that the chip exists." 1

Eleven cycles versus ninety cents

Grinberg's technical case is specific: he counts cycles and puts interrupt overhead on RV32E at 38 cycles, against 27 on the Cortex-M0, which he calls the competing cheap 32-bit core, an eleven-cycle gap 3. He documents compressed store instructions whose byte offsets reach zero through three, where Cortex-M0 reaches zero through thirty-one 3.

Then the reply prices the argument. A dollar part against a ten-cent part is a ninety-cent gap per student; the freight to get either one to Trinidad starts at sixty dollars 1. Run the classroom arithmetic: silicon for thirty students costs US$3 on ten-cent parts and US$30 on one-dollar parts. The cheapest freight bill Subero quotes is double the dollar-part class's entire silicon budget and twenty times the ten-cent one. Freight is flat per order, so the chip price is the only line that scales with headcount: sixty dollars, the bottom of Subero's band, buys the processors for twenty classrooms of thirty on ten-cent parts, or two classrooms on dollar parts. Per silicon dollar, ten students sit on RV32EC for every one on ARM. In Subero's framing, that gap decides whether thirty students each get their own chip or thirty students watch one demo board 1.

Digikey and Mouser free shipping does not reach him, and a PCB company weighing sponsorship declined over his location alone 1. His priority order is blunt: whether hardware can reach the desk at all comes before how elegant the silicon is once it arrives 1.

One desk, three price points, one ISA

Grinberg's central claim is that what a high-end CPU needs and what a small cost-saving microcontroller core needs are diametrically opposed, so no single ISA can serve both ends 3. Subero's counterargument is the parts on his desk:

• CH32V003: the ten-cent RV32EC with sixteen registers, no multiplier, no divider, machine mode only, 2KB of SRAM, 16KB of flash. Subero has shipped two products on it, a bin monitor and an agricultural door controller 1.
• CH32H417: a dual-core microcontroller with a QingKe V5F core at 400MHz and a V3F at 144MHz, 896KB of SRAM, and USB 3.2. Subero has run a web browser on it, and facial recognition in under 150KB of RAM 1.
• Baochip-1x: a VexRISC-V design with an MMU, open from silicon to operating system, running the Xous microkernel and seL4 1. WIRED covered it as the "mostly" open source chip inside the DEF CON 34 badges 4.

The sharpest technical point follows from the last bullet: when Grinberg lists privilege separation among the things the cheap end does not need and therefore does not get, Subero points out that on RISC-V it is a checkbox in the privileged spec 1.

The silicon shipped before the argument did

• July 31, 2026: WIRED reports 27,000 DEF CON badges carry the Baochip-1x, a "mostly" open source RISC-V microcontroller 4.
• August 14, 2026: Grinberg's essay draws a front-page Hacker News thread; Zeli summarizes the discussion in Japanese that day 5 2 1.
• August 16, 2026: the reply lands from Trinidad and Tobago, from the author of that badge chip's bare-metal C SDK 1.

Sixteen days separate the badge silicon from the reply, with the same ISA on both sides of the gap.

For builders and funders, the exchange redraws the market map. The students Subero wants to teach, in Nigeria and Bangladesh and everywhere else the industry does not think about when it writes its blog posts, are the audience for whom the ten-cent part is the whole decision 1. Grinberg's verdict assigns credit: RISC-V wins the cheap space despite the design. A freight invoice assigns access. Both essays end at the ten-cent chip; whether it is the ISA's basement or its front door depends less on the spec than on the shipping bill.